Self-aligned contact (SAC) capping refers to forming an electrical insulating layer on a metal gate of a fin field effect transistor (FinFET). Technology scaling requires smaller and smaller integrated circuit (IC) architecture. As integrated circuits become smaller, the individual circuit components become closer together. In the case of FinFETs, as the integrated circuits become smaller, for example, into 10 nm architecture and beyond, the gate of the FinFETs becomes very close to the trench silicide contacts (TS, local interconnects). The local interconnects provide electrical connections to components on one layer of an integrated circuit. For example, local interconnects may connect source, drain, and gates of different FinFETs on one level of an integrated circuit.
In most integrated circuit designs, the local interconnects are electrically isolated from the gate of the FinFETs. In this case, an SAC cap is formed on the gate. The SAC cap is a dielectric material disposed on the gate that provides electrical isolation between the local interconnects and the gate. With an SAC cap present, the local interconnect can be disposed on the FinFET without shorting the gate. However, in some integrated circuit designs, some of the local interconnect must be electrically connected to some of the gates.
In order to form an electrical connection between a gate with an SAC cap and a local interconnect, a portion of the SAC cap on the gate is removed and a second conductor is placed on the integrated circuit to form an electrical connection between the gate and the local interconnect. As discussed above, an SAC cap is conventionally used when the local interconnects and the gate are very close. In some cases, the local interconnects may cover a portion of the SAC cap on the gate. In this case, it is difficult to remove a portion of the SAC cap by etching because the local interconnect and the SAC cap include different materials. Etching can only remove a portion of the SAC cap not covered by the metal local interconnect. If only a small portion of the SAC cap is removed, it becomes even more difficult to dispose the second conductor through the etched SAC cap to the gate. This process may lead to a poor connection with the gate that may reduce chip yield and increase the number of future failures of the resulting integrated circuit.